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W9825G6JH
1. GENERAL DESCRIPTION
W9825G6JH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
4M words ? 4 banks ? 16 bits. W9825G6JH delivers a data bandwidth of up to 200M words per
second (-5). To fully comply with the personal computer industrial standard, W9825G6JH is sorted into
the following speed grades: -5, -5I, -6, -6I, -6A, -6K, -6L, -75 and 75L. The -5/-5I grade parts are
compliant to the 200MHz/CL3 specification (the -5I industrial grade, which is guaranteed to support
-40°C ≤ T A ≤ 85°C). The -6 grade parts is compliant to the 166MHz/CL3 or 133MHz/CL2 specification.
The -6I/-6A/-6K/-6L grade parts are compliant to the 166MHz/CL3 specification (the -6I industrial
grade, -6A automotive grade which is guaranteed to support -40°C ≤ T A ≤ 85°C). The -6K automotive
grade, if offered, has two simultaneous requirements: ambient temperature (T A ) surrounding the
device cannot be less than -40°C or greater than +105°C, and the case temperature (T CASE ) cannot
be less than -40°C or greater than +105°C. The -75/75L is compliant to the 133MHz/CL3 specification.
The -6L and 75L parts support self refresh current I DD6 max. 1.5 mA.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9825G6JH is ideal for main memory in
high performance applications.
2. FEATURES
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3.3V ± 0.3V Power Supply
Up to 200 MHz Clock Frequency
4,194,304 Words ? 4 Banks ? 16 Bits Organization
Self Refresh Mode: Standard and Low Power
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8 and Full Page
Burst Read, Single Writes Mode
Byte Data Controlled by LDQM, UDQM
Power Down Mode
Auto-precharge and Controlled Precharge
8K Refresh Cycles/64 mS, @ -40°C ≤ T A / T CASE ≤ 85°C
8K Refresh Cycles/16 mS, @ 85°C < T A / T CASE ≤ 105°C
Interface: LVTTL
Packaged in TSOP II 54-pin, 400 mil - 0.80, using Lead free materials with RoHS compliant
* Not support self refresh function with T A / T CASE > 85°C
Publication Release Date: Mar. 13, 2014
-3-
Revision: A09
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